SDL 3.0
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Go to the source code of this file.
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#define | SDL_CACHELINE_SIZE 128 |
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int | SDL_GetNumLogicalCPUCores (void) |
int | SDL_GetCPUCacheLineSize (void) |
SDL_bool | SDL_HasAltiVec (void) |
SDL_bool | SDL_HasMMX (void) |
SDL_bool | SDL_HasSSE (void) |
SDL_bool | SDL_HasSSE2 (void) |
SDL_bool | SDL_HasSSE3 (void) |
SDL_bool | SDL_HasSSE41 (void) |
SDL_bool | SDL_HasSSE42 (void) |
SDL_bool | SDL_HasAVX (void) |
SDL_bool | SDL_HasAVX2 (void) |
SDL_bool | SDL_HasAVX512F (void) |
SDL_bool | SDL_HasARMSIMD (void) |
SDL_bool | SDL_HasNEON (void) |
SDL_bool | SDL_HasLSX (void) |
SDL_bool | SDL_HasLASX (void) |
int | SDL_GetSystemRAM (void) |
size_t | SDL_GetSIMDAlignment (void) |
#define SDL_CACHELINE_SIZE 128 |
CPU feature detection for SDL.
These functions are largely concerned with reporting if the system has access to various SIMD instruction sets, but also has other important info to share, such as system RAM size and number of logical CPU cores. A guess for the cacheline size used for padding.
Most x86 processors have a 64 byte cache line. The 64-bit PowerPC processors have a 128 byte cache line. We use the larger value to be generally safe.
Definition at line 54 of file SDL_cpuinfo.h.
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Determine the L1 cache line size of the CPU.
This is useful for determining multi-threaded structure padding or SIMD prefetch sizes.
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Get the number of logical CPU cores available.
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Report the alignment this system needs for SIMD allocations.
This will return the minimum number of bytes to which a pointer must be aligned to be compatible with SIMD instructions on the current machine. For example, if the machine supports SSE only, it will return 16, but if it supports AVX-512F, it'll return 64 (etc). This only reports values for instruction sets SDL knows about, so if your SDL build doesn't have SDL_HasAVX512F(), then it might return 16 for the SSE support it sees and not 64 for the AVX-512 instructions that exist but SDL doesn't know about. Plan accordingly.
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Get the amount of RAM configured in the system.
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Determine whether the CPU has AltiVec features.
This always returns false on CPUs that aren't using PowerPC instruction sets.
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Determine whether the CPU has ARM SIMD (ARMv6) features.
This is different from ARM NEON, which is a different instruction set.
This always returns false on CPUs that aren't using ARM instruction sets.
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Determine whether the CPU has AVX features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has AVX2 features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has AVX-512F (foundation) features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has LASX (LOONGARCH SIMD) features.
This always returns false on CPUs that aren't using LOONGARCH instruction sets.
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Determine whether the CPU has LSX (LOONGARCH SIMD) features.
This always returns false on CPUs that aren't using LOONGARCH instruction sets.
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Determine whether the CPU has MMX features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has NEON (ARM SIMD) features.
This always returns false on CPUs that aren't using ARM instruction sets.
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Determine whether the CPU has SSE features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has SSE2 features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has SSE3 features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has SSE4.1 features.
This always returns false on CPUs that aren't using Intel instruction sets.
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Determine whether the CPU has SSE4.2 features.
This always returns false on CPUs that aren't using Intel instruction sets.